1. Field of the Invention
The present invention relates to a phase comparing circuit. More specifically, the present invention relates an improved circuit configuration for a phase comparing circuit suited for a lock detecting circuit of a phase locked loop.
2. Description of the Prior Art
Recently radio receivers employing a so-called digital frequency synthesizer using a phase locked loop as a local oscillator have been proposed and put in practical use. FIG. 1 shows a block diagram of such a radio receiver employing a digital frequency synthesizer as a local oscillator. Referring to FIG. 1, a tuning and detecting circuit 100 is connected to receive a high frequency signal received by an antenna AT and to provide an audio signal output. The tuning and detecting circuit 100 is structured to comprise a voltage controlled oscillator 1 as a local oscillator. The output signal from the tuning and detecting circuit 100 is applied to an audio amplifier 101, where the signal is amplified. The output of the audio amplifier 101 is applied to a speaker 102. As well known, in a digital frequency synthesizer radio receiver, a local oscillator is implemented by a voltage controlled oscillator, which is connected as part of a phase locked loop such that the oscillation frequency is controlled by the phase locked loop.
The phase locked loop shown in FIG. 1 comprises a phase comparator 5 structured to compare the phase of the output of a frequency divider 2 for frequency dividing at a given frequency division rate 1/n the output of the reference oscillator 3 the oscillation frequency of which is fr and the phase of the output .theta.V of a programmable frequency divider 4 frequency dividing at a variable frequency division rate 1/N the output of the above described voltage controlled oscillator 1 oscillating at the frequency F0. Comparator 5 produces a voltage signal proportional to the phase difference, which is applied to a low pass filter 6, where the phase difference output signal is filtered to provide a direct current output, which is fed back to the voltage controlled oscillator 1 as a voltage control signal. In such a phase locked loop, the oscillation frequency f0 of the voltage controlled oscillator 1 and the oscillation frequency of the reference oscillator fr meet the relation F0=N/n.multidot.fr, if and when the phase locked loop is in a stabilized condition or in a phase locked state. In order to change the local oscillation frequency, it is necessary to change the frequency division rate of the programmable frequency divider. Accordingly, the data concerning the broadcasting frequencies of various broadcasting stations is stored in advance in a memory 7. The data corresponding to the broadcasting frequency of a desired broadcasting station is selectively read out from the memory 7, responsive to selection of the desired channel by a channel selection circuit 8, and is supplied to the programmable frequency divider 4 such that the frequency division rate by the frequency divider 4 is set to a desired value, whereby preset channel selection of a desired broadcasting station can be achieved. If desired, the data as read from the memory 7 is displayed by a display 9, whereby the frequency as received is displayed.
In such frequency synthesizer radio receivers, fluctuation of the source voltage, noise in the phase locked loop, and the like could cause a phase difference between the reference frequency signal .theta.R as frequency divided by the frequency divider 2 of the output from the reference oscillator 3 and the frequency signal .theta.V, as frequency divided by the frequency divider 4, of the output from the voltage controlled oscillator 1 in association with the broadcasting frequency. This phase difference causes the phase locked loop to be unlocked. However, an error voltage associated with the said phase difference is applied to the voltage controlled oscillator 1, whereby the phase locked loop is locked again. In general, if and when the phase locked loop is unlocked because of a low frequency noise, the phase difference between the frequency signals .theta.V and .theta.R is relatively small and the phase locked loop is readily locked again, without causing a substantial affect on an audio circuit. On the other hand, if and when the receiving frequency is changed to select a desired broadcasting station, for example, a longer time period, referred to as a lock up time, is required until the phase locked loop is locked again and a noise other than a desired sound is heard from the speaker.
According to a conventional approach, therefore, when a phase difference exceeding a predetermined value occurred between the frequency signals .theta.V and .theta.R, i.e. the phase locked loop is in an unlocked state, the signal associated with the phase difference is withdrawn by a low pass filter 10 and the output VUL of the low pass filter 10 is applied to a display 11 to display the unlocked state and is also applied to the audio amplifier 101 to achieve a muting operation.
FIG. 2 shows a schematic diagram of a conventional lock detecting circuit of a phase locked loop utilizing such a low pass filter. Referring to FIG. 2, if and when no phase difference exists between the frequency signals .theta.R and .theta.V to be applied to the phase comparator 5, the output of the phase comparator 5 becomes zero and the terminal voltage of a capacitor 12 is the high level, while the output VUL of an inverter 13 representing an unlock detected output is the low level. If and when a phase difference exists between the frequency signals .theta.R and .theta.V, an MOS transistor 14 is rendered conductive during a time period corresponding to a phase difference responsive to the output of the phase comparator 4. This has the result that the capacitor 12 is discharged with a time constant determined by a conduction resistance value RT of the MOS transistor 14 and the capacitance value C of the capacitor 12. If and when the terminal voltage of the capacitor 12 is decreased lower than the threshold level of the inverter 13 through the above described discharging operation of the capacitor 12, the output VUL of the inverter 13 representing an unlock detected output is reversed to the high level, thereby to indicate an unlocked state of the phase locked loop. The MOS transistor 14 is reversed to a non-conduction state after the same is rendered conductive during a timing period corresponding to the above described phase difference and as a result the capacitor 12 is charged with a time constant determined by a resistance value R of a resistor 15 and the capacitance value C of the capacitor 12. If and when a phase difference still exists even upon receipt of the following pulse signal, the MOS transistor 14 is again rendered conductive and the capacitor 12 is discharged. In other words, according to a conventional lock detecting circuit utilizing a low pass filter, an unlocked state of the phase locked loop is detected in the form of discharging of the capacitor 12, whereby the state is stored for a time period corresponding to the charging time constant of the capacitor 12, which means that the conventional lock detecting circuit achieves two functions of lock detection and lock storing.
Meanwhile, it is necessary to make large to some extent the charging time constant of the capacitor 12, thereby to make large a storing time period. Thus, even when a phase difference is detected with respect to the frequency signal .theta.R at a given time point and the output VUL of the inverter 13 is reversed to the high level the terminal voltage of the capacitor may not be increased to reverse the output VUL of the inverter 13 to the low level until the following pulse signal .theta.R is received and the phase difference is detected again with respect to the said pulse. In general, it is necessary to increase the charging time constant of the capacitor 12 to be more than ten times larger than the cycles of the frequency signals .theta.R and .theta.V. This means that the capacitance value of the capacitor 12 must be increased. On the other hand, from the standpoint of the detecting sensitivity, i.e. the possible detectable minimum phase difference between the frequency signals .theta.R and .theta.V, an increase of the capacitance value of the capacitor means an increase of a discharging time constant and a decrease of the detection sensitivity. Accordingly, in a conventional lock detecting circuit employing a low pass filter, either a detecting function or a storing function had to be sacrificed. Another problem caused by an increase of the capacitance value of the capacitor 12 by preferring the storing function to the detecting function makes it difficult to fabricate the capacitor 12 of a large capacitance value when the phase locked loop and the lock detecting circuit is implemented in an integrated circuit.